1. Field of the Invention
The present invention relates to semiconductor devices and methods for forming semiconductor devices such as field effect transistors. More particularly, the invention relates to forming doped polysilicon layers in gates of field effect transistors.
2. Description of Related Art
High-k (dielectric constant) dielectric materials have been used to replace silicon oxide/nitride as the gate dielectric in MOSFET (metal-oxide-semiconductor field-effect transistor) devices as the size of MOSFET devices continually becomes smaller and smaller. The high dielectric constant of the high-k dielectric material allows increased gate capacitance while inhibiting leakage due to tunneling. New issues and/or problems arise as the designs of structures using high-k dielectric materials, the processes for forming such structures (e.g., gate layer formation during gate first high-k metal gate (HKMG) processes), and the uses of such structures continue to change. Thus, there is continuing development of new solutions to overcome some of these issues and/or problems.
One issue that may arise in certain MOSFET devices (e.g., PFETs (PMOS field effect transistors)) formed using HKMG processes is the presence of high gate series resistances at one or more interfaces in the device. The high gate series resistance (e.g., on the order of MΩ, 10 MΩ, or more in resistance) in the transistor may not cause failure of the transistor but may slow down the transistor or device to unacceptable or undesirable levels. If a semiconductor device has multiple PFET transistors that are designed to operate in connection with each other, having even one PFET transistor with high gate series resistance can slow down the semiconductor device to unacceptable levels regardless of the total number of PFET transistors (even on the order of hundreds or thousands of PFET transistors on a single device).
A potential cause for the high gate series resistance may be a lack of doping near the interface between the gate layer (e.g., the polysilicon layer) and the gate stack layer (e.g., the metal stack and dielectric layer) in the PFET transistor. The lack of doping near the interface may be caused by insufficient diffusion of the dopant during annealing of the gate layer, especially for polysilicon gate layers formed from amorphous silicon implanted with dopants. The lack of doping at the interface between the gate layer and the gate stack layer may form a Schottky diode at the interface. The Schottky diode at the interface may increase resistance at the interface and slow down operation of the PFET transistor (e.g., slow down turning on of the PFET transistor).